National_Catalogues: An Extraction-Based Verification Methodology for MEMS
Title:
An Extraction-Based Verification Methodology for MEMS
Identifier:
ADA500899
STOAbstractExternal:
Micromachining techniques are being increasingly used to develop miniaturized sensor and actuator systems. These system designs tend to be captured as layout, requiring extraction of the equivalent microelectromechanical circuit as a necessary step for design verification. This paper presents an extraction methodology to (re-)construct a circuit schematic representation from the layout, enabling the designer to use microelectromechanical circuit simulators to verify the functional behavior of the layout. This methodology uses a canonical representation of the given layout on which feature-based and graph-based recognition algorithms are applied to generate the equivalent extracted schematic. Extraction can be performed to either the atomic level or the functional level representation of the reconstructed circuit. The choice of level in hierarchy is governed by the trade off between simulation time and simulation accuracy of the extracted circuit. The combination of the MEMS layout extraction and lumped-parameter circuit simulation provides MEMS designers with VLSI-like tools enabling faster design cycles, and improved design productivity.
STOAuthorExternal:
CARNEGIE-MELLON UNIV PITTSBURGH PA DEPT OF ELECTRICAL AND COMPUTER ENGINEERING, Baidya, Bikram, Gupta, Satyandra K., Mukherjee, Tamal
STOClassificationExternal:
STOKeywordsExternal:
*MEMS(MICROELECTROMECHANICAL SYSTEMS), CANONICAL REPRESENTATION, FUNCTIONAL ELEMENTS, ATOMIC ELEMENTS, FINITE ELEMENT ANALYSIS, BOUNDARY ELEMENT ANALYSIS
STOPublisher:
USA
Language:
English
STOReportSource:
http://www.dtic.mil/docs/citations/ADA500899
Published:
7/30/2001
Created at 11/9/2016 3:26 PM by System Account
Last modified at 11/9/2016 3:26 PM by System Account
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